module Mux(data0, data1, ctrl, outData);
    input wire[31:0] data0, data1;
    input wire ctrl;
    output reg[31:0] outData;

    always @(ctrl, data0, data1)
    begin
        case(ctrl)
            1: outData <= data1;
            0: outData <= data0;
            default: outData <= 32'hffffffff;           
        endcase 
    end
endmodule